|
Abstract: New SoC designs are needed to integrate more logic and analog features in order to lower system cost. Freescale Semiconductor's approach for the automotive market is to integrate a single silicon chip that includes a full system: multicore, SRAM, flash, and analog IP components, including the power management system.
Introduction
The Freescale 32-bit automotive microcontroller unit (MCU) products are now moving into their fifth generation. In an effort to make electronics feature more affordable and power efficient, new MCU generations have been moving to smaller transistor geometry. At the same time, fuel efficiency and low emission constraints have led to increased requirements on sensor speed and accuracy, computational power and code complexity, so the total device area seemingly stays the same.
While the amount of digital circuitry increases exponentially, the analog portions of the system-on-chip (SOC) become a larger impact to the complete device area. This represents both a risk and an opportunity for area efficient smart analog IP's. The current generation of Freescale MCUs, operating in harsh environments up to 150°C, integrates a new power management controller (PMC). Major challenges in IP design and system integration will be discussed in next sections.
Figure 1: MPC5674F block diagram |
MPC5674F overview
The MPC5674F is a new MCU developed primarily for high end automotive applications such as
direct-injection diesel engines (Figure 1). The MPC5674F is based on a dual-issue 32-bit Power Architecture TM e200z7 core, along with a dual enhanced timing processor unit programmable coprocessor capable of independent timing operations on 64 channels with no interaction required from the main processor core.
For a complete SoC, the MPC5674F includes 4 Mbytes on-chip flash, 256 Kbytes of on-chip
general purpose SRAM, 32 Kbytes of Harvard architecture cache, four serial interfaces, four CAN interfaces, four SPI interfaces, one FlexRay interface, system timers, 32 dedicated independent timing channels and four A/D converters with 64 conversion channels (eight differential channels with programmable gain and eight decimation filters).
Power management controller
The initial requirements for the PMC were including a small, robust architecture with low I/O pin count and flexible extended features. Other requirements include: no start-up power sequences, compatibility with previous MCUs and real-time monitoring of critical analog signals. The block diagram is reported in Figure 2.
In this part, a low power POR monitors PMC main supply Vddreg and it enables a small regulator from Vddreg level (2.7 to 5.5 V) to Vdd12, a PMC internal supply compatible with core devices. Vdd12 is used to power PMC blocks that do not require high voltage: a low voltage band-gap, a buck regulator and LVIs. If compared to a high voltage solution, area savings are relevant, despite the added regulator, mostly due to the fact that all control signals from the CPU will not require high voltage level shifters.
Since the PMC deals with several power domains, during start-up it is desirable that supplies can
rise in any sequence. This is achieved by implementing a domino power-up of internal regulators, according to the states of POR's and LVI's. Once the analog core supply Vdd12 has come up, the low voltage band-gap reference is started. Then the PMC enables the 3.3V regulator if the supply VDDREG is above 4V, and a core regulator controller is chosen according to the voltage level on the dedicated I/O pin. Internal blocks start in a controlled way thanks to soft start-up circuitry, therefore start-up currents will be limited and well diodes will be reverse-biased at any time without triggering latch-up.
Each POR and LVI monitors its corresponding supply, guaranteeing the correct range of operation of the device. For each LVI, threshold voltage and desired response (reset or interrupt) might be programmed by software. Total power consumption from core supply (1.2V -5%/+10%) at 150°C can be as high as 1000 mA, and the maximum core voltage variation allowed by specification is less than 180mV including LVI's deviation. A careful trade-off between operating levels, decoupling capacitance and regulator bandwidth and stability adds challenges to the PMC and regulators design.
|
