Synopsys accelerates circuit simulation performance

Venice, Florida — Synopsys, Inc. has announced a new multi-core initiative to deploy advanced parallel, threaded and other optimized compute technologies across its Discovery^TM Verification and Galaxy^TM Design platforms, and Design for Manufacturing (DFM) solutions. The initiative aims to enable integrated circuit (IC) design companies to easily maximize the throughput of their multi-core compute infrastructure to reduce time-to-results (TTR). This initiative builds on Synopsys' proven multi-processor and network-distributed electronic design automation (EDA) solutions, including the VCS® functional verification solution with native testbench technology for compute farms and the Proteus lithography solution offering near-linear scalability. Additional multi-core-enabled solutions will be delivered throughout 2008.

Multi-threaded HSPICE
HSPICE is the first product released that takes advantage of the new software architecture. According to the company, new multi-threading capabilities in this release of the HSPICE simulator speed up circuit simulation by taking advantage of new multi- core computer architectures. As a result, circuit designers can now run HSPICE post-layout simulations up to three times faster on single-core processors and up to six times faster on four-core processors.

The newest version of the HSPICE simulator delivers improvements in the symbolic DC operating point convergence algorithm, transient time-step control, netlist parsing and model performance. These enhancements accelerate overall simulation throughput on single-core computers.

Previously, HSPICE multi-threading capabilities allowed circuit designers to quickly simulate large pre-layout designs. With this release, Synopsys has extended HSPICE multi-threading capabilities to enable simulation of large post-layout designs containing in excess of a million resistive and capacitive parasitic effects. As a result of these enhanced multi-threading simulation capabilities, most fully extracted post-layout designs can now be simulated, according to the company, an order of magnitude faster than previously possible.

See also:
Demystifying multithreading and multi-core

and
Speaker cites multicore benchmarking challenges

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