The past decade has seen massive growth in portable products. When combined with time-to-market pressures and the increasing need for flexibility, this growth makes new low-power field-programmable gate arrays (FPGAs) ideal platforms for the development of these consumer and industrial applications. Historically, FPGAs and programmable logic devices (PLDs) have been notoriously power hungry. Fortunately, this paradigm is changing. Advances in FPGA design have dramatically lowered the power consumption of new devices, making them an ideal solution for battery-powered applications.
At the same time, the embedded market continues to move toward 32-bit processing to handle the increasing computational needs of today's cutting-edge designs. It has been difficult to find a broadly used, industry-standard processor that can be implemented efficiently in the course-grained architecture of FPGAs. This has changed with the availability of the FPGA-optimized ARM Cortex-M1 processor. When coupled with power-efficient, flash-based FPGAs, the 32-bit Cortex-M1 offers designers a flexible system construction platform for building portable products that offer maximum battery life.
The new power paradigm
The relevant physics of integrated circuit power consumption is changing as process geometries shrink. In the past, dynamic power dominated and the power supply could be lowered with every successive process shrink. Lower voltages meant less dynamic power, and the trend continued in the right direction, but lowering operating voltages is no longer possible. Additionally, the physics of semiconductors at smaller process geometries has dramatically increased static power related to leakage. Process technology has shrunk to the point that static power is becoming a greater issue for portable applications than dynamic power. This is especially true when maximum temperatures are considered where leakage currents can increase by an order of magnitude or more.
Due to the increasing impact of leakage and ongoing efforts to increase power efficiency, non-volatile flash-based FPGAs have been able to approach and, in some cases, beat application-specific integrated circuit (ASIC) and application-specific standard product (ASSP) power efficiencies. These technical changes and innovations, such as new power optimization modes, have enabled FPGAs to demonstrate dramatically lower static power consumption. This makes them an ideal solution for portable applications that must also balance flexibility and the ability to accommodate the ever-changing standards for end products.
Combined with reduced dynamic power, their surprisingly low static power numbers enable flash-based FPGAs to provide lower total system power in many cases than ASIC and ASSP solutions. As a result, the perceived FPGA power penalty is much greater than what is seen today in actual designs, and when the flexibility of FPGAs is taken into account, it is a wonder that ASICs and some ASSPs still find a place in the market.
The new generation of low-power FPGAs
A new generation of single-chip, nonvolatile flash-based FPGAs eliminates the power up current spike associated with the configuration of traditional FPGA technologies. As a result, programmable logic can achieve new levels of power efficiency. Now, sophisticated low power and sleep modes that were only previously available on ASSPs are showing up on flash-based FPGAs.
Traditional SRAM-based FPGAs lose their configuration while in sleep mode and therefore require reconfiguration, which takes hundreds of milliseconds and consumes hundreds of milliwatts of power, so low power modes and especially sleep modes are superfluous. Flash-based FPGAs, on the other hand, offer a variety of low power modes and can be put to sleep and woken up just like ASSPs, because the live-at-power-up feature enables immediate operation of the device when power returns. Furthermore, new technologies (like Flash*Freeze from Actel) are enabling easy entry and exit from the ultra-low power modes while retaining SRAM and register data.
Another important low power feature of flash-based FPGAs is that they don't require additional support devices to function properly. Often, SRAM-based FPGAs need an external memory to store the configuration bitstream, a CPLD to act as a configuration controller, and a device to trap brownouts and power glitches so the FPGA will be properly reset and reconfigured. In addition to the added board space and cost, each extra component adds to the overall power profile of SRAM FPGA solutions, these added components make system power-up more complex. Flash-based FPGAs do not require external components to operate, enabling them to provide more than five times longer battery life in portable applications than other low power programmable logic devices.
