BENGALURU, India — Researchers from the Indian Institute of Technology (Mumbai) have devised an approach for hardware generation from high-level programs that they say accommodates design reuse. The team's AHIR hardware intermediate representation acts as a transition layer between software compilation and hardware synthesis, leveraging optimizations in the software compiler flow while letting the low-level synthesizer explore options for application-specific implementations, the researchers said.
"Two operations become possible: the reuse of computational resources across modules in the design and the generation of an application-specific memory subsystem for faster data access," the researchers said in a paper presented here at the VLSI Design meeting.
Many attempts have been made to create a path from high-level programming languages to hardware specifications. Some either extend or restrict the C language to enable programmers to write synthesizable C code. Some disallow pointers and extend the syntax for arrays designed for DSP algorithms, while in others compilers cannot optimize the code, since rearrangements in the statements violate the timing models.
The Phoenix project uses an intermediate representation (IR), Pegasus, for a compiler flow from C to hardware. The data flow representation uses handshakes to exchange data between operators designed as micropipeline states.
Like Pegasus, the hardware intermediate representation proposed by the Indian Institute of Technology uses handshakes to transfer data across operators. But while Pegasus assumes unlimited hardware, AHIR anticipates hardware reuse by decoupling the control and data flows in the program, according to the researchers.
AHIR is claimed to provide a synthesis path that builds on existing high-level compilers. The representation is generated by a compiler back end, independently of the input language used. The program may have been written in any kind of programming environment, such as sequential or concurrent execution.
The design is expressed only in terms of operations, and it mandates minimal timing constraints on the implementation. The synthesizer can explore implementation options within those constraints. "AHIR thus positions itself as a convenient transition point that glues together high-level compilation and low-level synthesis flows," the researchers said.
A compiler flow using AH IR has been implemented using the LLVM Compiler Infrastructure, with the first step being a low-level virtual machine back end that produces a hardware specification in AHIR as an XML file.
The researchers established a complete flow from a high-level C program to a hardware description using AHIR. "The development process begins with an executable source program that is verified at a software level," according to the paper. "The IR presents a complete specification of the hardware, while the simulator provides information about memory accesses and operator utilization to aid in hardware optimization. Hardware created in this manner may not compete with hand-designed implementations in performance, but the savings in the overall design cycle are large enough to offset the performance overheads."
The decoupled nature of the specification allows transformations that optimize the resulting hardware. Computing resources can be shared across modules by generating a joint specification for multiple data paths. The joint specification can reuse resources, since AHIR allows arbitrarily complex elements in the data path, the researchers said.
A transformation can map operations across the original data paths to such elements in the combined data path, provided the symbolic handshakes are correctly interpreted. The memory system can also be implemented independently and can be arbitrarily complex in order to improve access times and reduce bottlenecks, the team said.
