Austin, Texas — This may be the year that three-dimensional chips emerge from the R&D stage. But for real progress to be made in connecting circuits in the vertical dimension, large semiconductor companies will have to lead the way, experts said, since only they have both the design and manufacturing expertise required to pull it off.
Meanwhile, several startups have blazed a trail in 3-D technology, said Ken Monnig, associate director of the interconnect program at International Sematech. But the technology can't grow unless products are developed for it, he noted. "If 3-D is going to take off, what needs to happen is that a large IDM [integrated device manufacturer] needs to develop a specific product, targeted for 3-D technology," Monnig said.
International Sematech, which counts nine large semiconductor companies as its members, is trying to provide an industry framework for 3-D development. The organization launched an internal 3-D study program that aims to create a road map for development of the manufacturing infrastructure required to connect chips vertically.
"Our vision is to create tables, so the vendors can have a clear understanding — marching orders if you will — of what the industry wants, said former Bell Labs interconnect researcher Susan Vitkavage. "Our goal is to do that this year," she said.
Also, Vitkavage said Sematech is creating economic models to assess the costs associated with the additional processing steps required to make 3-D circuits. "Costs need to be detailed. We want to break out those costs by product types, including memories and MPUs. We need to understand 3-D for each product type," she said.
Sematech is working with a variety of equipment vendors, including those that manufacture tools used for alignment, wafer thinning, chemical-mechanical polishing, silicon-through-sili-con via etching and copper deposition. The consortium will help assess equipment performance — similar to what the organization did for low-k characterization — including the alignment tolerances required for high-performance parts. Sematech also is working on ways to assure reliability, developing "torture tests" to check the bonds between two chips.
The term 3-D in this context refers to chips that are connected with thousands of vertical connections, some as small as a micron in diameter. The terminology of vertical chips is somewhat confusing. "Stacked" packages are used commonly in cell phones and other space-constrained products, with SRAM, flash and DRAM dice stacked and connected with wire bonding. Other vendors connect microcontrollers with memory through wires or bumps at the package level, creating what are called system-in-package solutions.
Thousands of connections
While stacked packages have a limited number of wires connecting each chip on the periphery, 3-D chips can have tens of thousands of connections per millimeter.
Over the past five years, interest has turned to 3-D connections as a means of reducing latency between memory and logic, or to connect one die made with a nonstandard process with a CMOS chip. Several 3-D chips made by startups connect optoelectronics fabricated in a gallium arsenide process with logic and memory, for example.
Early forays into 3-D technology have been made by a number of companies. Ziptronix Inc. (Morrisville, N.C.), for one, announced last September that it was shipping a chip, made for "a major networking customer," that vertically connected a flash memory die with a second die containing programmable logic and microprocessor circuitry.
Ziptronix has developed a bonding process that strips back the oxide to expose the metal interconnects, which are connected vertically through a covalent bonding process. The approach can be used to connect known-good dice in a die-to-wafer connection process, or through wafer-scale bonding.
