Advanced interconnects drive intelligent vision applications: Part 2

Socket monitoring via smart interconnects
Recognizing the need to monitor in-band and out-of-band data for values, latencies, and any other data that is potentially relevant for both debug and optimization, the Sonics Multi-Service Exchange (SMX^TM) architecture includes features that enable data flow control, access, and monitoring of parameters. In the SMX architecture, there are basically three classes of interconnect structures; Crossbar Exchanges, Shared Link Exchanges, and Extended Link exchanges, each with their own features and analysis requirements.

SMX Crossbars allow the fastest unimpeded connectivity, while Shared Links require less overhead of additional gates and also support the optimal data flow by quality of service (QoS) selection. Extended Links support more widely separated cores. Related Sonics products also provide connectivity of slower peripheral or optimize scheduling to improve the efficiency of DRAM controllers and the effective bandwidth of external DRAM. The following figure may help clarify the SMX internal structure description.

SMX allows several methods of accessing performance and analysis information from the interconnect structure. Most commonly, for high-level exploration and optimization, SystemC-type levels of abstraction are utilized. Sonics IP generates SystemC models and RTL (register transfer level) from the same configuration files, insuring functional equivalence. Additionally, interfaces and SystemC models of Sonics IP integrated with high level ESL (electronic system-level) tools like those from CoWare, are verified by both parties.

However, MobilEye also wished to do extensive profiling of bus and processor activity under various scenarios. In addition, developers wanted to provide a robust test bench for verification and future debug because of the challenging requirements and increases in performance under a very aggressive schedule. For this reason, MobilEye chose to work with First Silicon Solutions (FS2) to enhance bus monitoring capabilities to facilitate the more extensive desired analysis.

Indeed, those who have experienced HMP (heterogeneous multi-processor) designs with different speeds and multiple video streams will recognize the common challenge of efficiently accessing DRAM. In high volume, cost-sensitive applications, radically increasing device pin count and widening buses for external parallel memory is not an option. Competitive designs require efficient implementations.

The interconnect environment
The SMX Crossbar and Shared Link Exchanges present a complex data communications network. The FS2 MIPS32 34Kf cores operate at twice the system clock frequency and interfaces to the SMX over a 64 bit open core protocol (OCP2.0) bus. SMX includes resources for resolving the mixing of bus widths and speeds across different blocks, which simplifies efficiency and optimization of performance with regards to different data rates, clock rates, etc. of the system cores. Indeed, the following options are also provided: