Editor's note: In this second installment of a four-part series on debugging FPGA designs, author Brad Frieden explains that when debugging an FPGA-based system, it can be very helpful to look at key signals inside the FPGA correlated with those in the rest of a system. When equipped with an FPGA-focused application called the FPGA Dynamic Probe that is used to select internal FPGA signals of interest, an Agilent mixed-signal oscilloscope, with both analog and digital inputs, can provide such insight. See also Part 1: Using a core-assisted approach to accelerate the debug of FPGA-based DDR II interfaces.
Today's digital designs often find significant portions of their functionality implemented with FPGAs. When debugging such systems, one challenge can be gaining the necessary visibility to key signals inside the FPGAs, since there is usually a significant pressure to minimize the use of FPGA pins for debug, rather than for the design. Often in debug, there's also the need to view both internal FPGA functional signals, like state machines, while also carefully viewing timing and signal integrity characteristics of digital signals on the FPGA interface as it connects to the rest of the system. The latter is typically looked at with digitizing oscilloscopes. In this article, we will look at an approach that allows the combination of these measurements through the use of an Agilent mixed signal oscilloscope (MSO) in conjunction with an application add-in called the FPGA Dynamic Probe.
A debug example
A good example to illustrate the capabilities of the MSO with the FPGA Dynamic Probe capability is the debug of a packet communications system, as shown in Fig 1. A state machine drives the process of sending out packetized 16 bit data along with a Transaction ID, which is essentially a packet number. Parallel data is serialized, sent on a serial channel, de-serialized and brought into a "Monitor". A second state machine at the Monitor drives the process of receiving the packets, stripping off the data and Transaction IDs so they can be pulled off to external memory, but also generating Acknowledge IDs that are fed back to the transmit side to say "I got the data, keep it coming!" At first boot up, unfortunately, something's going wrong with data coming into the Monitor.
1. Packet communications system block diagram.
(Click this image to view a larger, more detailed version)
The designer only has 16 pins available on his FPGA for debug, so he (or she) has placed a Mictor connector on the board and routed those FPGA pins over to it. The MSO connects to that Mictor connector with its 16 digital input channels. In this case an Agilent MSO8000 series scope is used as shown in Fig 2. There are some additional signals that are part of the functioning design that are also routed to the Mictor connector. He has also accessed a serial signal external to the FPGA in the design with an active probe on the MSO's analog channel.
2. An Agilent Infiniium mixed-signal oscilloscope coupled with
the FPGA Dynamic Probe Application.
The goal is to track down the specific conditions under which the problem of moving data is occurring, or perhaps to even identify the root cause.
Making the best use of 16 available pins
One of the first considerations the designer has to make is what signals are important to view in order to validate system operation or uncover improper operation. In this case, he wants to see the state machine that's driving the transmission of packets, as well as the data and Transaction IDs. He'd also like to see receive state machine, data, and Acknowedge ID signals over at the Monitor side. Since he hand coded his 8B/10B encoder, he wouldn't mind looking at some of the data in and out of that. Finally, he has a master synchronization state machine that he'd like to see boot up.
The problem is, since he only has 16 available pins for debug on his FPGA, short of placing his own MUX into the design, he's run out of pins even if he only wanted to view key signals at the transmitter. And if the designer did put his own MUX into the design, he'd have to craft a way to select the signals he wanted and keep track of them.
Instead, he'll use a measurement core that allows him to have a more automated way to select between various signals of interest right from his Agilent Mixed Signal Oscilloscope. More specifically, he can define four signal banks, each 16 bits wide, where each individual bank selects the transmit, receive, encoder, and synchronizer signals of interest. He can then choose which signals he wants to look at on the MSO.
He can also probe up to four other signals external to the FPGA with the MSO's analog inputs to view timing, jitter, or signal integrity of those signals. For example, since his serial data is running at 200 MHz, he can probe that nicely with a 1.5 GHz bandwidth active probe on a 1 GHz bandwidth MSO.
Measurement core insertion
It's really simple to insert the measurement timing or state cores using the Xilinx Core Inserter that's part of Xilinx ChipScope Pro. Signals of interest are selected from the Structure/Nets window and the designer simply clicks the Make Connections button. For a state core, the main clock is defined that drives the synchronous systems, and the Xilinx design tools will ensure that valid signals are output on each clock for capture by the MSO. A view of this signal selection menu is shown in Fig 3. Now the design can go back through place and route so that this measurement core is included.
3. ChipScope Pro Core Inserter signal selection menu.
(Click this image to view a larger, more detailed version)
How to set up the FPGA Dynamic Probe
From the MSO the designer can now set up the FPGA Dynamic Probe. The steps required to do this include the following:
- Launch the FPGA Dynamic Probe application running either on a PC remotely connected to the MSO, or on the Infiniium MSO itself.
- Make a connection to the JTAG chain.
- Download the design with a core into the FPGA.
- Perform import bus and signal names from Core Inserter .cdc file.
- Perform auto pin mapping of the FPGA to the MSO.
- Select the signal bank of interest to be viewed on the MSO.
Pin mapping is an automated process facilitated by the FPGA Dynamic Probe application. Each FPGA debug pin has a training sequence signal placed on it and the MSO searches through all of its input channels until that training sequence signal is found. The MSO builds up a table to keep track of how the FPGA is probed. The results of this "pin mapping" are shown in Fig 4. Once this is done, the application can set up the MSO to properly assign MSO channels.
4. Auto pin-mapping.
At this point measurements can be made on the internal FPGA signals that make up a signal bank time correlated to the external analog signals on the four analog input channels.
